GPCIe is a PCI Express IP core which provides a simple
interface to the backend logic designed by the user. Combining GPCIe
with the backend logic, the user can easily implement an interface to
other PCI Express devices without detailed knowledge about PCI
Express protocol.
GPCIe Single Project package (hereafter GPCIe SP) is a developer suits
that bundles GPCIe (a PCI Express IP core), reference design, device
driver, control library. It is inteded for use in a single project,
and the bundled IP core supports only one FPGA device family.
The package also includes technical support and design consultation
with our technical staff, which are especially helpful for developers
new to the PCI Express devices.
Bundled Items
This package includes:
Technical support for 1 year.
Reply to question about usage of GPCIe.
Offer device and design suitable for the user's needs.
Free update of the package.
Reply to question about details of GPCIe implementation,
including modification of the VHDL source code.
GPCIe IP Core itself (with VHDL source code)
HIB (Host Interface Bridge)
HIB (Host Interface Bridge) is a logic that resides at the topmost layer
of the IP core logic. It encapsulate complex PCI Express protocol
to provide a simple interface to the user-side logic.
Comes with the VHDL source code, device drivers for Linux and Windows and
a control library (with C source code).
HIB supports DMA.
HIB supports PIO write combining usig Page Attribute Table.
The device driver for Windows is built with Windows Driver Foundation.
Functions as an End Point. Does not function as a Switch nor a
(Root port of ) Root Complex.
"Application Layer" built over the three PCI Express layers,
namely, Tarnsaction Layer, Data Link Layer, and Physical Layer,
provides a simple interfece to the backend logic designed by the
user. The layer also provides PCI configuration registers and DMA
controllers. These feature enables the user to implement an interface
to other PCI Express devices, without detailed knowledge about the
Transaction-Layer protocol.
All logics are described in VHDL. Various parameters including
revision (Gen1/Gen2), link width, max payload size, and flow-control
buffer size, can be given as generic parameters.
NOT FULLY COMPLIANT with the PCI Express
Specification. There exist some functions which are currently not
implemented into GPCIe, nevertheless the Specification requires. These
functions are mainly for error detection and recovery, for power
management, and for PCI Express compliance test.
Supplied with VHDL source code, so that the user can apply
arbitrary modification to the function.
The write performance is for programed I/O (PIO) write to a memory
page to which write-combining attribute is set. The read performance
is for direct memory access (DMA) write from GPCIe to the host computer.
The red curves are for measured values. The blues are for
theoretical estimate.
Measured on a host computer with Intel X38 chipset.
GLink is our original serial interface specification. It has a quite
simple protocol stack that consists of the Physical Layer of the PCI
Express (PHY PCS) and a few control signals. Since there's virtually
no latency to interpret header of the data packet, it can achieve
close-to-peak throughput even at rather small data size (~100byte).
Also it requires quite small amount of logic resources compared to
that of PCI Express.
Some of our products
adopts GLink for interconnect among multiple FPGAs.
GPCIe is a PCI Express IP core which provides a simple
interface to the backend logic designed by the user. Combining GPCIe
with the backend logic, the user can easily implement an interface to
other PCI Express devices without detailed knowledge about PCI
Express protocol.
GPCIe Basic can be used without fee under the license agreement.
Supported FPGA device is limited to Altera's Stratix II GX and Arria GX only.
Please use GPCIe SP for other devices.
A development kit (
summary and user's
guide) is freely available. Plase ask support@kfcr.jp for download.
The development kit includes:
GPCIe IP Core itself (with VHDL source code)
HIB (Host Interface Bridge)
HIB (Host Interface Bridge) is a logic that resides at the topmost layer
of the IP core logic. It encapsulate complex PCI Express protocol
to provide a simple interface to the user-side logic.
Comes with the VHDL source code, device drivers for Linux and Windows and
a control library (with C source code).
HIB supports DMA.
HIB supports PIO write combining usig Page Attribute Table.
The device driver for Windows is built with Windows Driver Foundation.
Functions as an End Point. Does not function as a Switch nor a
(Root port of ) Root Complex.
"Application Layer" built over the three PCI Express layers,
namely, Tarnsaction Layer, Data Link Layer, and Physical Layer,
provides a simple interfece to the backend logic designed by the
user. The layer also provides PCI configuration registers and DMA
controllers. These feature enables the user to implement an interface
to other PCI Express devices, without detailed knowledge about the
Transaction-Layer protocol.
All logics are described in VHDL. Various parameters including
revision (Gen1/Gen2), link width, max payload size, and flow-control
buffer size, can be given as generic parameters.
NOT FULLY COMPLIANT with the PCI Express
Specification. There exist some functions which are currently not
implemented into GPCIe, nevertheless the Specification requires. These
functions are mainly for error detection and recovery, for power
management, and for PCI Express compliance test.
Supplied with VHDL source code, so that the user can apply
arbitrary modification to the function.
GPCIe can freely be used under the following license agreement.
Do not modify the value (1B1Ah) of vendor ID initially set to
address 00h of PCI configuration register.
Any products obtained using GPCIe, including logics designed with
GPCIe, hardwares which GPCIe is configured into, and research outcomes
obtained using such logics or hardawres, must explicitly describe the
fact "the product is obtained using PCI Express IP Core GPCIe
developed and distributed by K&F Computiong Research Co.", in the
product itself, user's guide, published paper, or any substantial part
of the product.
In no event arising from, or in connection with GPCIe, shall
K&F Computiong Research Co. be liable for any claim, damages or
other liability,
As a general rule, you are prohibited from using, selling or any
activity related to GPCIe inside the United States. If you plan to do
so, you need to ask the authors for the permission.
All copies and forks of GPCIe shall subject to this license agreement.
Offers technical support and design consultation with our technical
staff for 472,500 JPY/year, which are especially helpful for
developers new to the PCI Express devices.
